Ferroelectric nonvolatile memories have been attractive because they can have performance advantages over current memories such as DRAM, E2PROM, and flash. For example, ferroelectric nonvolatile memories can have higher write endurance, lower write voltage, lower power consumption, and enhanced radiation-hardness.
Ferroelectric properties are thought to result from noncentral symmetric arrangement of ions a crystal unit cell, which produces an electric dipole moment. Titinates such as BaTiO3 and PbTiO3 are typical ferroelectric materials exhibiting ferroelectricity with Ti off-center in a perovskite unit cell. Among the many different ferroelectric materials, Pb(ZrTi)O3 (PZT) with a Zr to Ti ratio of between 0.4 to 0.7 are perhaps the most commonly used in a variety of applications. Their use in nonvolatile memory devices was made practical by introduction of oxide intermediate layers between PZT and Pt electrodes to solve a fatigue problem. However, the memory density of such ferroelectric memories is still limited by the incompatibility of PZT deposition processes with silicon semiconductors. Lead and lead oxides found in PZT materials pose additional problems as a choice in the memory device industry due to environmental concerns.
SrBi2Ta2O9 (SBT) ferroelectric materials are reduced fatigue and lead free compositions that have been considered for use in ferroelectric memories. However, SBT requires an undesirably high deposition temperature ranging from about 750° C. to 800° C. Furthermore, the current SBT high density FeRAM (with 1T1C or 2T2C structures) is not a desirable material for mainstream memory chips due to large chip size and high manufacturing costs.
Recently, a single transistor memory cell (ferroelectric-gate FET) has been successfully demonstrated by COVA Technologies. The one transistor (1T) memory cell is expected to considerably reduce cell area, possibly making FeRAM cost competitive. Metal ferroelectric insulator semiconductor (MFIS) 1T cell structures can be preferred due to their simpler structure and manufacturing processes. MFIS buffer layers can be desirable because they provide low interface states and a good interface with silicon. However, insertion of a MFIS buffer layer can also have undesirable effects, such as, e.g., a shortened data retention period and low operational voltage drops in the buffer layer. Therefore, when using MFIS buffer layers, the ratio of dielectric constants between the gate-ferroelectric and buffer dielectric layer (∈f/∈b) should be low enough for applied voltage not to drop over the barrier layer during low voltage operation.
The YMnO3 family has a favorably low dielectric constant and has been considered for use in MFIS ferroelectric switching devices. However, such materials have not provided good ferroelectric properties in their thin film forms, even though they show acceptable ferroelectric properties in their single crystal forms. One problem might be that the mixed valence of Mn+2, Mn+3 and Mn+4 in the YMnO3 thin films can cause a serious electrical leakage when provided as a capacitor material.
In view of the above, a need exists for a stable ferroelectric material with a low dielectric constant and low leakage. It would be desirable to have ferroelectric materials requiring relatively low processing temperatures and without toxic metal constituents. The present invention provides these and other features that will be apparent upon review of the following.